1. Technical Field
The present invention generally relates to electrostatic discharge (ESD) protection circuits and, more particularly, to ESD protection circuits using triple well semiconductor devices residing in an integrated circuit.
2. Related Art
As electronic components are getting smaller and smaller along with the internal structures in integrated circuits, it is getting easier to either completely destroy or otherwise impair electronic components. In particular, many integrated circuits are highly susceptible to damage from the discharge of static electricity. Electrostatic discharge (ESD) is the transfer of an electrostatic charge between bodies at different electrostatic potentials (voltages), caused by direct contact or induced by an electrostatic field. The discharge of static electricity, or ESD, has become a critical problem for the electronics industry. Device failures are not always immediately catastrophic. Often the device is only slightly weakened but is less able to withstand normal operating stresses and, hence, may result in a reliability problem. Therefore, various ESD protection circuits must be included in the device to protect the various components. Multiple considerations are taken into account during the design of such ESD protection circuits.
With system-on-a-chip (SOC), advanced CMOS and high level integration, different circuit and system functions are integrated into a common chip substrate. The industry has expended considerable efforts to prevent noise created by one circuit from infecting another circuit. The industry has used triple well technology to help provide this noise isolation. Unfortunately, with the introduction of triple well technology, several problems must be addressed with respect to ESD networks.
CMOS technology traditionally provided single well or double well isolation. In single well technology, an n−well was placed in a p−type substrate. In dual well technology, a p−well was placed in a p−type substrate as well. For both single and double well, the ESD protection networks were kept the same since the transition from single well to double well did not alter the electrical connections needed for either MOSFET-based ESD protection or diode-based ESD protection networks. The first problem results from the transition from single- or dual-well technology to a triple well technology. The triple well technology requires a region which electrically isolates both the p−well and the n−well from the substrate.
Another problem arises when mixed voltage applications are used. Mixed voltage applications are where the peripheral power supply voltage is different from the native core voltage power, or the input pad voltage exceeds the native core voltage power supply. Mixed voltage applications require unique ESD networks that don”t turn on below the applied voltage condition. In triple well technology, this is a concern since structures must be able to be biased without inadvertent turn-on during the functional regime. ESD networks in a mixed voltage environment may not be able to use MOSFET structures due to electrical overstress of the MOSFET transistor. MOSFET electrical overstress occurs above the native power supply condition due to dielectric overstress.
It would, therefore, be a distinct advantage to have a triple well technology ESD network that could overcome the above noted problems. The present invention provides such an ESD network